1. Field of the Invention
The present invention relates to a large scale integrated circuit (LSI) for controlling motor rotation speed, and more particularly, to an LSI circuit suitable for digital control of motor rotation speed employing two counters for counting a number of clock pulses.
2. Description of the Related Art
In recent years, it has been essential to build computer systems which are more and more compact. Accordingly, in order to miniaturize circuit boards in computer systems, the circuits are generally fabricated in LSIs. This need for miniaturization also exists for motor rotation speed control circuits which keep the rotational speed of a motor of a magnetic disk device, etc. at a target speed.
For controlling the motor rotation speed, clock pulses, originally provided for an associated main computer system, have been utilized for measuring cycle time of the motor rotation. Among several methods of digitally controlling the motor speed, there has been devised a method employing two counters. A prior art circuit configuration employing two counters is shown in FIG. 1. In FIG. 1, reference numeral 24 denotes a first counter to which a reset signal RST is input at a clear terminal CLR for each rotation of the motor, and clock pulses of a predetermined constant frequency are input at a clock terminal CLK. On receiving the reset signal RST, the first counter 24 resumes counting the clock pulses after clearing the previously counted number of clock pulses until the next reset signal is received, so as to obtain a count-number proportional to a cycle time T.sub.n of the motor rotation. The first counter 24 is provided with a first AND gate 26 for detecting a target count-number N.sub.0 which corresponds to the motor's target speed according to the clock pulse number counted thereby. Input terminals of the first AND gate 26 are selectively connected to parallel bit-outputs, composing the target count-number N.sub.0, of the first counter 24. Assuming a target motor rotation cycle time corresponding to the target motor speed is T.sub.0, the number to be counted, i.e. the target count-number N.sub.0, is given as follows: EQU N.sub.0 =T.sub.0 /clock pulse cycle time
Thus, the moment that the counted clock pulse number reaches the target count-number N.sub.0, the first AND gate 26 is enabled and outputs a target speed detection signal GJUST.
The first counter 24 is further provided with a second AND gate 28 for outputting a fast-speed detection signal GFAST and a third AND gate 30 for outputting a slow-speed detection signal GSLOW, as described below.
Assuming that a detection range of the fast-speed signal and the slow-speed signal are set at, for example, .+-.0.5% of the target count-number N.sub.0, input terminals of the second AND gate 28 are connected selectively to the bit-outputs of the first counter 24 such that a 0.5% lower count-number (N.sub.0 -.DELTA.N, where .DELTA.N=(0.005)(N.sub.0)) than the target count-number N.sub.0 is detected. Similarly, input terminals of the third AND gate 30 are connected selectively to the bit-outputs of the first counter 24 such that 0.5% higher count-number (N.sub.0 +.DELTA.N) than the target count-number N.sub.0 is detected.
FIGS. 2 and 3 explain operations of the first counter 24 and the three AND gates 26, 28 and 30 of FIG. 1.
When the motor rotation speed is slower than the target rotation speed, as illustrated in FIG. 2, the motor rotation cycle time T.sub.n, which is determined by the reset signal RST, is longer than the target motor speed rotation cycle time T.sub.0. Consequently, before receiving the next reset signal, the fast-speed detection signal GFAST is output when the count-number of the counter 24 reaches (N.sub.0 -.DELTA.N). Next, the target speed detection signal GJUST is output when the count-number reaches the target count-number N.sub.0. Finally, the slow-speed detection signal GSLOW is output when the count-number reaches (N.sub.0 +.DELTA.N). The motor speed control circuit controls the motor speed so as to increase the motor speed depending on the amount of the deviation D of the next reset signal RST from the target speed detection signal GJUST and also issues signals which, for example, control other related circuits, etc., according to the slow-speed detection signal GSLOW.
When the motor rotation speed is fast, as shown in FIG. 3, the motor rotation cycle time T.sub.n determined by the reset signals RST is shorter than the target motor rotation cycle time T.sub.0. Therefore, the first counter 24 is reset by the reset signal RST before reaching the target count-number N.sub.0. Consequently, the target speed detection signal GJUST will not be output.
Therefore, in the prior art circuit of FIG. 1, there are further provided a D flip-flop 34 and a second counter 32 so that the target speed detection signal can be output even when the motor speed is faster than the target speed. The D flip-flop 34 outputs its Q output, as a reset signal RST.sub.b, when it receives a first pulse of the fast-speed detection signal GFAST from the second AND gate 28 for each rotation cycle. The reset signal RST.sub.b is input to the second counter 32 at a clear terminal CLR, and clock pulses are input at a clock terminal CLK. Furthermore, preset-data terminals A, B, C, D, . . . of the second counter 32 are externally set by an application of a high level (H) signal or a low level (L) signal thereto so as to set the count-number .DELTA.N, which is to be counted after the output of the fast-speed detection signal GFAST. At the time the second counter reaches the count-number .DELTA.N, the target speed detection signal GJUST should be output by the first AND gate 26. Instead, since the motor speed is fast and the first counter has been reset, the second counter 32 outputs a carry signal CARRY when the count-number reaches the preset count-number .DELTA.N. This carry output is referred to as a second target speed detection signal GJUST-II, which functions in place of the lost target speed detection signal GJUST.
The operation of the prior art circuit configuration can be summarized as follows. When the motor rotation speed is fast, the fast-speed detection signal GFAST is first output by the second AND gate 28 when the first counter 24 has reached the count-number (N.sub.0 -.DELTA.N), and the D flip-flop 34 is set in synchronization with the clock pulse so that its Q output is an L signal. Then the second counter 32 is cleared to start counting the clock pulses. Upon counting to the preset count-number .DELTA.N, the second counter 32 outputs the carry signal CARRY as the second target speed detection signal GJUST-II.
However, a problem exists in the above-described prior art motor rotation speed control circuit. When the target rotation speed is to be modified, the count-numbers to be detected by the first, second and third AND gates 26, 28 and 30 and the preset count-number of the second counter 32 must all be modified. Such modifications of the count-numbers can be done by only modifying the connections of the data pins leading out of the first and second counters 24 and 32. Therefore, in the case in which entire control circuits are fabricated in an LSI, the data pins of the first and second counters 24 and 32 must lead out of its package so that connections can be changed as needed externally in order to meet modification requirements. This causes an increase in the number of the external data pins. Accordingly, the size, as well as the cost, of the LSI package is increased.